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MicroAlchemy
Rapid silicon prototyping

Foundry

Planar 1µm shuttle — quick-turn

Low-volume planar CMOS with optional bipolar/MEMS options. Configure wafers and process stack to get a quick estimate.

Capabilities (1µm+ planar)

  • Min feature size: 1.0 µm (drawn)
  • Metal: 2 layers (Al), top thick option
  • Gate oxide: 25–40 nm (thick I/O option)
  • Device types: CMOS, analog I/O, optional NPN
  • Channel resistance targets: < 150 Ω/□ poly; < 25 Ω/□ metal
  • Thermal budget: up to 1050°C, 3 anneal cycles
  • Wafer size: 200 mm; dicing available (known-good-die)
  • Passivation: SiN with pad openings; ESD diodes on request

Order parameters

Process summary

  • Min feature: 1.0 µm
  • Metal layers: 2
  • Gate oxide: 35 nm
  • Anneal cycles: 2
  • Device mix: CMOS

Estimate

$24000

For 2 wafers · standard turnaround

Packaging: Whole wafer

Notes

  • Rush adds premium and pulls TAT to 4–5 weeks.
  • NPN/MEMS variants add extra mask steps.
  • Dicing/QFN is pilot-scale; expect limited yield tuning.